Bits, Bytes, and Words: Computer Memory Units Explained

Modern computers address memory in bytes (groups of 8 bits), with each byte having a unique address. The CPU can read/write a 'word' (a fixed number of bits, e.g., 32 or 64 bits) from any memory address in constant time. With a 32-bit word size, the maximum addressable memory is 2^32 bytes (about 4 gigabytes), which limited older computers. With 64-bit word size, the limit is about 20 exabytes, which is more than all data stored by Google.

Word size denotes the number of digits a CPU can process at one time, with modern processors typically using 8, 16, 24, 32, or 64 bits. Many historical word sizes included 8, 9, 10, 12, 18, 24, 36, 39, 40, 48, and 60 bits. A 32-bit computer can address 2^32 bytes (4 GB), but this relationship between word size and address size does not always hold. The 16-bit Intel 8086 supported 20-bit addressing via segmentation, accessing 1 MB rather than 64 KB. All Intel Pentium processors since the Pentium Pro include physical address extensions mapping 36-bit physical addresses to 32-bit virtual addresses. In theory, 64-bit computers can address 2^64 bytes, but practical memory is limited by the CPU, memory controller, or PCB design.

CPU word size determines the amount of data the CPU can process at once. A 64-bit CPU has a word size of 64 bits (8 bytes), allowing addressing from 0 to 2^64-1. Modern 64-bit CPUs use only 48 bits for memory addressing, enabling approximately 282 terabytes of addressable memory. Of this, about 141 terabytes is allocated for user space programs while the remaining 141 terabytes is reserved for kernel use.

Pointers are traditionally considered difficult in C programming, but their basic concept is straightforward: they are simply an alternative way of looking into memory. When used precisely as pointers into memory rather than for complex arithmetic, they are easy to understand and maintain. Understanding pointers requires knowledge of memory organization, including word size, endianness, and alignment. Computer memory can be conceptualized as a bag of words where data is stored and retrieved. Each piece of information has a specific size (width) and memory has finite capacity determined by hardware. RAM (Random Access Memory) is temporary volatile storage that loses data when power is turned off, but is significantly faster than hard disk storage. Memory sizes use binary prefixes: 2^10 = 1024 is 1 Kilo, 2^20 = 1,048,576 is 1 Mega, and 2^30 = 1,073,741,824 is 1 Giga. A pointer is a variable that stores an address rather than actual data. When declared but not initialized, a pointer contains an undefined value and attempting to access it will crash the program. To initialize, use the address-of operator '&' (e.g., 'p = &x'). The dereference operator '*' accesses the value at the memory address stored in a pointer. As long as the pointer is not changed, *p and the variable it points to are completely interchangeable. The word size is the practical unit of data storage in memory, directly related to CPU register size. Modern CPUs typically have 32-bit or 64-bit registers, making words 32 or 64 bits respectively. The C language standard defines minimum sizes: char at least 8 bits, short at least 16 bits, int at least 16 bits, long at least 32 bits, and long long at least 64 bits. The actual sizes depend on the compiler and platform. The ILP32 data model (used in 32-bit Windows, Linux, and Mac OS) has int, long, and pointers all at 32 bits. The LP64 data model (used in 64-bit Linux) has int at 32 bits, long and pointers at 64 bits. The LP64 model was necessary to support memory addresses beyond 4GB. Word size directly affects the range of numbers: 8-bit signed ranges from -128 to +127, while 32-bit signed ranges from approximately -2×10^9 to +2×10^9. The 32-bit limit was a major constraint as memory grew beyond 4GB. Moving to 64-bit architectures and 64-bit long types (on Linux) provides ranges of approximately ±10^19, sufficient for most practical applications.

CPU memory addressing limitations are determined by the width of the address bus. A 32-bit address bus can address up to 4GB of memory, meaning any memory beyond this limit cannot be accessed by the CPU. This limitation affects the maximum usable memory in a computer system. To access more memory, processors with wider address buses (like 64-bit processors) are required.

Byte order, or endianness, refers to the way computers store multi-byte data in memory, with big-endian format storing the most significant byte at the lowest memory address and little-endian format storing it at the highest address; while both formats function equally well in modern 64-bit systems, big-endian is mandated for network data transmission (network byte order) to ensure consistent data exchange between different computer architectures.

Endianness determines how multi-byte numbers are stored in memory: big-endian stores the most significant byte first, while little-endian stores the least significant byte first. This concept emerged in the 1960s-70s when computing standards were not established, leading companies like Intel (little-endian x86) and Motorola (big-endian 68000) to differentiate themselves. Computers store numbers in binary using bytes (8 bits each), with larger numbers requiring multiple bytes. For example, 324,000 (hex: 13579BDF) is stored as 13 57 9B DF in big-endian but DF 9B 57 13 in little-endian. The term derives from Jonathan Swift's Gulliver's Travels. Endianness matters when transferring data between hardware with different endianness, between computers over networks (TCP/IP uses big-endian), loading/saving data to disk, and debugging on little-endian systems. A critical pitfall is passing floating-point numbers to integer byte-swapping functions, which causes implicit type conversion that corrupts data.

Endianness refers to byte ordering in memory storage. Little-endian stores the least significant byte at the lowest memory address (Intel architecture), while big-endian stores the most significant byte first. For example, the 32-bit value 0x12345678 would be stored as 78 56 34 12 in little-endian memory (address order: low to high), but as 12 34 56 78 in big-endian. Intel processors use little-endian, meaning values appear reversed when viewed in memory compared to their register representation.

Endianness refers to the byte ordering convention used to represent multi-byte data in computer memory, where big-endian systems store the most significant byte first (like humans write numbers) and little-endian systems store the least significant byte first; this distinction is crucial for data interpretation, especially in network communications where RFC 793 mandates big-endian format for headers, and understanding that endianness applies only to multi-byte values (not single bytes or bit-level ordering) helps avoid common debugging pitfalls.

Endianness refers to the byte order used to store multi-byte data types in memory, where little-endian systems store the least significant byte first and big-endian systems store the most significant byte first; when sending data over networks between systems with different endianness, programmers must convert data to network byte order (big-endian) using functions like htonl() and ntohl() to ensure correct interpretation across all platforms.

This section covers the core bitwise operations used in low-level programming. AND requires both bits to be 1 for a 1 result. OR produces 1 if either bit is 1. XOR produces 1 when exactly one bit is 1. NOT inverts all bits. Logical shifting treats bits as raw data, while arithmetic shifting respects signed integer representation. Rotation moves bits around the register without losing them, with left rotation moving the leftmost bit to the rightmost position and vice versa. Shifting left multiplies by 2, while shifting right divides by 2, providing efficient multiplication and division by powers of 2.

Six primary bitwise operations manipulate individual bits within words: AND (logical conjunction), OR (logical disjunction), XOR (exclusive or), NOT (inversion), and shifts (left/right movement). Each operation applies logic to corresponding bit pairs or single bits. Shifts move all bits while optionally filling vacated positions with zeros, ones, or rotated bits. These operations enable precise control over binary data representation and manipulation.

Bitwise operators (&, |, ^, ~, <<, >>) manipulate binary representations of integers at the bit level. AND (&) performs bit-by-bit comparison; OR (|) combines bits; XOR (^) toggles bits; NOT (~) inverts all bits; shifts move bits left/right. These operators enable efficient low-level programming tasks including setting/clearing individual bits in flags, device registers, and memory optimization. Practical applications include hardware control, embedded systems programming, and performance-critical code where direct bit manipulation improves efficiency.

Bit manipulation involves dealing with data in registers by changing individual bits rather than treating data as whole numbers. In an 8-bit register, bits are numbered 0-7 with values 1, 2, 4, 8, 16, 32, 64, 128 respectively. The difference between uppercase and lowercase letters in ASCII lies in bit 5 (value 32): 'A' (65) has bit 5 as 0, while 'a' (97) has bit 5 as 1. The AND operation checks if a specific bit is 1 or 0 by performing AND with a mask (e.g., AND with 32 to check bit 5). The OR operation sets a specific bit to 1 by ORing with a mask. The XOR operation inverts bits by XORing with 1 at desired positions. Two's complement represents negative numbers by inverting all bits and adding 1. Bit shifting moves bits left or right within a register. Left Shift (LSL) doubles the value: 6 (00000110) becomes 12 (00001100) after one shift, 24 after two shifts. Bits shifted out are lost, and 0s enter from the right. Right Shift (LSR) halves the value: 6 becomes 3, then 1. Fractional results are truncated. The number of shifts is specified in the instruction (e.g., LSL 3 for three left shifts). Shifting is limited by register size (e.g., 4-bit register holds 0-15).

Bitwise operators work on individual bits of numbers. AND (&): 0&0=0, 0&1=0, 1&0=0, 1&1=1. OR (|): 0|0=0, 0|1=1, 1|0=1, 1|1=1. XOR (^): 0^0=0, 0^1=1, 1^0=1, 1^1=0. NOT (~) inverts all bits. Left shift (<<) multiplies by 2^n, right shift (>>) divides by 2^n. These are essential for system programming, microcontrollers, and performance optimization.

Memory is organized in a hierarchy: registers (smallest, <1KB), cache memory (1KB-16KB), main memory (<16GB), and secondary memory (≥100GB). Cache memory has greater space than registers but less than main memory. Main memory has more space than cache but less than secondary memory. Secondary memory is used when smaller memories are insufficient (e.g., large programs or videos). The processor accesses data through this hierarchy: registers first, then cache, then main memory, then secondary memory, with each level backed up by the next larger level.

Memory hierarchy organizes memory from fastest/smallest/most expensive to slowest/largest/cheapest: CPU registers, Cache (L1, L2, L3), RAM, and Secondary Storage (HDD, SSD). RAM is volatile (data lost when power off), used as the computer's working desk for currently running applications. ROM is non-volatile, containing permanent boot instructions. Cache is built into the CPU, acting as a personal assistant storing frequently accessed data. The trade-off is: higher levels offer speed and cost but limited capacity, while lower levels offer capacity and low cost but slower speed. This hierarchy balances performance, size, and cost—no single memory type can be both as fast as SRAM and as cheap as SSDs.

This video explains the computer memory hierarchy, focusing on registers and cache memory. Registers are high-speed, volatile memory located within the processor with very low storage capacity and high cost. Cache memory serves as an intermediate buffer between the processor and RAM, storing frequently accessed data to improve performance. Cache memory is divided into three levels: L1 (smallest, fastest, inside processor), L2 (slower, can be in processor or motherboard), and L3 (largest, slowest, on motherboard). The processor accesses memory hierarchically: first L1, then L2, then L3, and finally RAM if data is not found in any cache. This hierarchical structure balances speed, cost, and storage capacity in computer systems.

The memory hierarchy organizes memory from fastest to slowest: registers (fastest, smallest capacity, located within CPU), cache memory (L1, L2, L3 levels serving as bridges between registers and main memory), main memory/RAM (large capacity, moderate speed), and secondary memory (hard disk, flash disk, CD with largest capacity but slowest speed). Cache memory levels vary in location—L1 typically integrated in processor, L2 on processor or motherboard, L3 for multi-core CPUs. Main memory (RAM) serves as primary working memory with gigabyte-scale capacity. Secondary memory communicates with main memory through the I/O module, which is necessary because secondary storage must be read first before data transfer.

Computer memory exists in three main locations: (1) Inside the CPU (registers and cache), (2) Main memory (RAM), and (3) Secondary storage (HDD, SSD). Registers are the fastest, allowing immediate read/write within a single clock cycle. Cache memory (L1, L2, L3) balances speed, capacity, and cost—L1 is fastest but smallest and most expensive, while L3 is largest but slowest and shared among cores. RAM is volatile (loses data when power is removed), while secondary storage is non-volatile. The CPU cannot directly address secondary storage; it treats such devices as input/output operations.