8259 Programmable Interrupt Controller | Features & Applications

[00:00:00]Do subscribe to Ekeeda channel and press bell icon to get updates about latest Engineering HSC and IIT-JEE Mains and Advanced videos.Hello Friends, In this video we will study about some of the features of the 8259 IC which is also known as the programmable interrupt controller or it's short for miss PIC so let's start with the topic.

[00:00:42]So we are going to study about the programmable interrupt controller PIC whose IC number is 8259 now we know that the 8085 Microprocessor it has 5 hardware interrupt pins and these hardware interrupt pins are drop rst seven point five six point five and five point five and int yard so if we write here in eight zero eight five five hardware interrupt pins are there and these five hardware pins are trap rst seven point five six point five and five point five and we have int R so these are the five Hardware interrupts in the eight zero eight five microprocessor now out of these five hardware and drugs the four hardware's in drop drop seven point five six point five and five point five they have the interrupt vector addresses or we can say that these four and graphs are the vectored in drops vector interrupts because for the interrupt service routine which is written at some memory location that address is known for these interrupts like for trap we have the address so these are the addresses where of the memory location where the interrupt service routine is written so whenever these interrupts are given to the microprocessor the microprocessor will jump to these memory locations and those memory locations instructions are written subroutine is written so that subroutine will be executed and again the microprocessor will continue to perform its main task okay so we can say that out of these five hardware and drop pins for hardware interrupts pins have addresses for their interrupt service routine whereas this high n TR this intra is a non vectored interrupts non-vector interrupt because it's vector address for the interrupt service routine is not known to the eight zero eight five microprocessor so when external devices needed which will provide the vector address for this int are interrupt okay and this external device will tell the microprocessor that what is the type of the interrupts which it has to execute and what is the address where the subroutine is returned okay so this external device we'll provide the type of the interrupt like the type of the interrupt related to it is from rst 0 2 is T 7 these are the restart instructions in the 8 0 8 5 microprocessor which are executed through this int our interrupt request signal ok this interrupt when this interrupt is given then these instructions will be executed okay so this external device it will provide the type of the interrupts and also the interrupt vector address so that becomes the function of the external device that it has to provide the type of the in drop and interrupt vector address to the eight zero eight five or to the microprocessor we can say okay so that is why there is a need of a device which will tell the microprocessor these things okay now let us come to the applications like where several number of input/output devices they want to communicate with the microprocessor so when there are number of input/output devices then and all the devices they want to transfer the data to the microprocessor in the interrupt driven data transfer mode so in this mode whenever any input/output device it want to communicate with the CPU or the microprocessor it is going to interrupt the microprocessor that I want to transfer the data and then communicate with me okay so if I say here that this is the microprocessor suppose 8 0 8 5 is there and there are several input/output devices now each of these input/output devices they want to communicate with the eight zero eight five okay they want to transfer the data now this data transfer will take place when every input/output device it will send an interrupt signal okay to the eight zero eight five and then eight zero eight five it has to check the priority that which of the so when these input/output devices they want to communicate with the eight zero eight five then they are going to send an interrupt request to the eight zero eight five that I want to complicate with it or I want to transfer the data to you okay now this is zero eight five it has to decide that which of the input/output devices it want to first communicate okay because there are many input/output devices it has to check the priority which of the input/output device is having the highest priority so I will first communicate with that and then according to the priorities it is going to transfer the data or it won't it will communicate with the input/output devices so this 8 0 8 5 it need to check the priorities and also it wants to have the interrupt signal from all these input/output devices ok so the 0 8 5 this microprocessor it becomes busy in this task to check the priorities to communicate with the these data so rather than becoming busy in this task of checking the priorities and of of negating with these input/output devices it uses a device which is known as the 8 to 5 9 programmable interrupt controller which controls all the interrupts operations of the microprocessor so that is why the need of an external device arises and this need is fulfilled by developing our controller programmable interrupt controller 8:00 to 5:00 9:00 okay so this 8:00 to 5:00 9:00 which is known as the programmable interrupt controller it controls all the input interrupt operations clock this 8 0 8 5 microprocessor when it is communicating with multiple interrupt systems like where it is having multiple interrupts then we can use this 8 2 5 9 I see this programmable interrupt controller okay so in this video we are going to study about some of the features of this programmable interrupt controller or p IC so if we talk about the features of this p IC its first use is that it is used to in handle all the interrupt operations of the microprocessor or we can say that it is used to relieve the microprocessor from the task of checking the priorities and handling the multiple interrupts okay so this controller it takes cares of a number of simultaneously occurring in drops the request means when there are many number of interrupt requests which are occurring at the same time so that type of interrupt request can be handled using this controller and also the type of the interrupt request means which type of interrupt is provided by the input/output devices the type and also the priority that which interrupts is having the highest fry T which is having the lowest by T and that is also decided by this controller so this controller takes cares of the multiple interrupts which are occurring in the processor okay so this controller it is basically relieving the microprocessor from these tasks okay now this programmable interrupt controller whose IC number is eight two five nine also known as P I seen this controller it can handle eight interrupt pins okay so eight input/output devices which are sending eight interrupt request to the microprocessor they can be handled through this eight two five nine so here if we have the micro processor zero eight five or any type of microprocessor is there so we will have this eight two five nine which is connected between the eight zero eight five and the input/output devices so here we can have eight input/output devices and this eight two five nine it has eight interrupt pins okay so it interrupts can be handled or interrupt request can be handled by this eight two five nine and this is similar to like earlier we were having four eight zero eight five we were having the int our line okay have even having interrupt request line so only one device can communicate with eight zero eight five but if we are using eight two five nine then eight interrupt pins or eight interrupt requests can be handled by the eight zero eight five just this eight two five nine it will decide the priority that which interrupt request is having the highest priority so that interrupt request will be first exist then second then third so in this way the variety is decided but if eight two five nine we are not using then there we will be having only int R and in case of eight zero eight six we have the int line so only bunny interrupt request can be handed back with eight two five nine it can handle a interrupt lines okay so this is one of the feature of this P I see now the second feature is that this eight two five nine it can be used with any type of microprocessor system like eight zero eight zero eight zero eight five eight zero eight six eight zero eight so all the versions of the microprocessor it can't work with okay so here we can write that eight two five nine can't work with h0h 0h0 eight five eight zero eight six and eight zero eight eight now this eight two five nine it was the older version the new version is eight two five nine a now the difference between eight two five nine and eight two five nine a is that if two eight two five nine can walk only with a 0 8 0 + 8 0 8 5 whereas a 2 5 9 can work with any of these 4 type of microprocessor systems with eight zero eight six and eight zero aided it can also work but it would it - five nine it cannot work so that is the only difference between the two versions 8 - 5 9 e it is an updated version or we can say it is a higher version of 8 2 5 9 next feature of 8 - 5 - that in a 0 8 5 micro processors we have the vector addresses ok and that is the problem we discussed that when we are having the int online then the interrupt vector address is not available ok if we see the addresses if we see the addresses of the so if we see the addresses of the interrupts which are there in the 8 0 8 5 I have told that you got trap rst seven point five six point five five point five they have the interrupt vector addresses which is already fixed but for int are the 0 8 5 need some external device which is going to provide the intra make interest ok now if you see the addresses you can see that all the addresses or all the interrupt service routines they are written on page number 0 0 okay this 0 0 it is showing the page number and this 2 4 3 C 3 4 to see it is showing the pop column number wrong number okay so this all these interrupt service routines they are written on the same page zero zero okay but if we are and this address for this int are it is provided by the external device and this external devices are P I see the programmable interrupt controller now this programmable interrupt controller can set the address of the interrupt request on any memory location okay four eight zero eight five we have suppose we are having the memory locations from 0 0 0 0 to F F F F this is the complete memory locations of 8 0 8 5 now this I to bite none it can place the Interop request or it can write the interrupt service routine at any of these memory locations okay but for the trap rst 7.5 the service routines they are written on the same page so that is the you use or that is the speciality of this a 2 5 9 programmable interrupt controller so I can write the feature of this that the 8 2 5 9 chip so this eight two five nine Jeff it convector an interrupt request anywhere in the memory map from zero zero zero H - f F F H in 1808 five microprocessor so anywhere in this memory map the vector request it kept the interrupt request it can't be vector or its service routine can't be returned at any memory location between this 0 0 0 to F F F H now this is eliminating the drawback that in the case of trap and rst seven point five six point five the surface routines they are written at on the same page zero zero okay now it's 0 8 5 microprocessor it is dealing with multiple interrupt systems where it is varied more to communicate with the several input/output devices and all the input/output devices they want to transfer the data in the interrupt data driven transfer mode okay so for then multiple interrupt systems are connected then microprocessor has to decide the priorities of the Indra that which interrupts is having the highest priority and which is having the lowest priority so that in the priority order of the interrupts their request will be exist by the microprocessor now this task when we are using the eight two five nine the eight two five nine it is going to decide the priorities of the interrupts so the microprocessor it is free from this task so that is the feature of eight two five nine that it can decide the priorities among the interrupt request the eight interrupt requests which are even to the microprocessor so it interrupt pins can be connected to eight to five nails so we can say that it can resolve eight levels of interrupt practice in a variety of moves and there are various types of modes of operation of 8:00 to 5:00 night so according to the modes of operation the priority levels can be decided so it is the feature that it can resolve eight levels of intra Fridays now these practice they can be changed when the interrupts request they are being accessed by the microprocessor means when the microprocessor is executing the service routine of an intra at the time of execution of the service routine also the priority of it drops can be changed means running status of the practice can also be changed like if we are running a in drug if the microprocessor it is rocking an intra pitch is having a highest priority in between the execution of its service routine the Kendra which is having the lowest priority can also be accessed okay so in this way this 8 to 5 minute can change the priority of the interrupt at any level okay at the time the service routine is executed at that time also the variety can be changed so the practice of interrupts it can be changed under running condition also now next feature is interrupts we can say that in case of a zero eight five we have also studied that the interrupts can be masked okay means if there are several interrupts which are simultaneously occurring at the microprocessor interrupt pins so out of those like for interrupt request are given one of them can be masked okay so this masking and unmasking of the interrupts it can be done through this eight two five nine I see also this masking of interrupts is done individually means the masking is not of the interrupts it is not interconnected that if this is mask this interruptus mic then other end of it can also be masked okay so this masking and unmasking of it drops it is independent of each other okay and every interrupts can be masked individually so through eight two five nine so just like the interrupts of the 8:08 5 the interrupt request through this 8 to 5 min it can also be masked individually now when multiple interrupts are given to the microprocessor then 8 2 5 9 suppose there are 4 in drop and it is executing one interrupts and one interrupts will be pending and one interrupt will be masked so the status of the interrupts that which is which interrupts is currently executed by the 8 2 5 9 which is pending and which of the interrupts are mask all these status of the interrupts it can be read at any time by the microprocessor if we are using this 8 2 5 9 p IC controller so the status of pending interrupts or in-service interrupts means the interrupts which are currently being executed by the microprocessor and the masked interrupts the interrupts which are past that when the first will be executed then the second will be executed okay those interrupts are masked interrupts ok they can be read at any time by the microprocessor and that is the one of the feature of 8 2 5 9 now when we were starting the eight zero eight five and drops you would have remembered that the eight zero eight five and drops then can be either level triggered or edge triggered some of them were level triggered and some of them were edge triggered okay now for those interrupts if triggering if it is or level triggered then only the level of the clock cycle means I got high level or low level it can trigger the interrupt and if it is an edge trigger then you leave that when this edge of the clock cycle is provided then only that interrupt will be given okay but if we are using this eight two five nine I see this p IC controller then the interrupt request they can be programmed either as an level trigger or either as a edge triggered okay so both type of triggering can't be provided to the interrupt request using this eight two five nine but if we are using eight zero eight five then means if we are using simply the microprocessor then we have to provide the triggering which is specified for that interrupt if the interrupt is level triggered that we have to provide lever triggering if the interrupt this edge triggered then we have to provide the edge triggering okay but eight two five nine it can program the interrupts either as a level trigger or as an edge trigger so this triggering it is decided by the eight two five nine there are various modes of eight two five nine in which the triggering is decided okay so here we can write that door eight two five nine so this 8 to 5 9 p IC controller it can be programmed to accept the interrupt request either as level triggered or edge triggered whereas it 8 0 8 5 the triggering is decided either a level or either a edge okay that is decided for the interrupts now with 8 2 5 9 we have the facility that I said that 8 to 5 minute can handle 8 in criminal pins ok means 8 interrupt requests can be handle at one time now if more than 8 interrupts requester we want then how we are going to do this we can cascade means we can connect more than two eight two five nine Isis and if you are connecting suppose we are connecting nine eight two five nine Isis then we can handle 64 and drop requests at a same time okay but if you are using only one than eight we are using like if it is one eight two five nine I see so it is going to handle eight and drops okay now if they want 64 interrupt requests then we are going to connect nine eight two five nine ICS okay eight eight two five nine ICS will be the slave Isis will be the master I see okay so in this way 64 interrupt requests can be handled at a by using the cascaded version means by using nine eight two five nine I see simultaneously so if required nine eight two five nine so if it is required then nine eight two five nine ICS they can't be cascaded in a master slave configuration to handle sixty-four interrupt inputs and in this configuration eight ICS will act as a slave Isis and what will act as a master Isis so the interrupts the input/output devices which are sending the interrupt request they will send their request to the slave eight to five nine and those slave it to five nine they are going to send the request to the master eight to five nine and this master eight two five nine I see is then going to give the int our request interrupt interrupt request to the microprocessor okay so the master eight two five nine I see it can directly send a request also or it will accept the request from the slave ICS and then it is going to give the request to the microprocessor this we will discuss in detail when we will study the modes of operation of eight two five nine so these were some of the features of a two five nine programmable interrupt controller which is also known as bi see we studied that this interrupt controller it controls the interrupts operations like it decides the priorities of the interrupt and it also provide the type of the interrupt the vector addresses to the microprocessor means this interrupt request line int are the address of the interrupts will be provided by the eight two five nine so this eight two five nine can be used whenever the microprocessor it is handling of multiple interrupt system okay so I hope that this topic is clear to you thank you