STM32 Timer Input Capture: PWM Frequency and Duty Cycle Measurement

The Auto-Reload Register (ARR) defines the counting period before overflow, with the timer period in seconds calculated as (PSC + 1) / Timer Frequency. The CR1 control register manages fundamental timer behavior: CEN enables/disables the counter, UDIS disables update events, URS determines update source (any event or overflow only), OPM enables One Pulse Mode for single-count operation, and ARPE enables buffer mode for ARR register application. Different timers may have CR1 or CR2 registers, requiring documentation review. The prescaler must be at least 1 to prevent division by zero. These registers enable precise timing control for various embedded applications.

STM32 timers have three essential configuration parameters: Counter Period (AutoReload Register) which sets the maximum counter value before it wraps around to zero; Prescaler which divides the input clock frequency to control how often the counter increments; and Counter Mode which determines whether the counter counts up, counts down, or uses center-aligned mode for symmetric waveforms.

The STM32 timer system uses a prescaler (PSC) to divide the system clock (e.g., 64MHz) into a slower counting clock, and a 16-bit counter that increments from 0 to ARR (Auto-Reload Register) before overflowing. The prescaler value must be calculated as (PSC + 1) because counting starts from 0. For example, with a 64MHz system clock, setting PSC to 6399 creates a 10kHz counting clock, and setting ARR to 9999 creates a 1-second overflow period. The timer can generate PWM signals by comparing the counter value against a Compare Capture Register (CCR), where the output pin changes state when the counter equals CCR. PWM duty cycle is controlled by the ratio of CCR to ARR, allowing precise control of average output voltage for applications like motor speed control and LED dimming.

A timer measures time by counting internal clock cycles and generates pulses or interrupts at predetermined intervals. A counter counts external clock signals input from outside the system. Despite different definitions, timers and counters share the same hardware implementation in microcontrollers. The AT Mega 128P contains 4 timer/counter units: Timer/Counter 0 and 2 are 8-bit devices, while Timer/Counter 1 and 3 are 16-bit devices. When operating as counters, timer/counter units receive external clock signals through dedicated input pins: Timer/Counter 0 uses T0SC1, Timer/Counter 2 uses T2, and Timer/Counters 1 and 3 use T1 and T3 pins. A prescaler divides the system clock frequency to reduce counting speed, with values of 1, 8, 32, 64, 128, 256, and 1024 available. Timer/Counter 0 uses five main registers: TCNT0 (8-bit counter, counts 0-255), TCCR0A (control register A), TCCR0B (control register B), OCR0 (output compare register), and TIMSK0 (interrupt mask register). Timer/Counters 0 and 2 share the same interrupt mask register (TIMSK0) and interrupt flag register (TIFR0).

Hardware timers are physical registers in microcontrollers that automatically count clock pulses from the crystal oscillator, incrementing with each clock tick and overflowing when reaching maximum values (255 for 8-bit, 65,535 for 16-bit); they enable precise time-based operations like generating delays, PWM signals, and triggering interrupts without blocking the main program loop, with prescalers (frequency dividers before the timer) extending the timer's range to measure longer time intervals, and postscalers (dividers after the timer) controlling interrupt frequency without affecting the timer's counting speed.

PWM is a fundamental technique in digital electronics using rectangular pulses with distinct on-time (pulse width) and off-time components. The complete cycle consists of both states, with cycle time being the total duration. Duty cycle quantifies the proportion of on-time relative to the full cycle, calculated as (Pulse Width/Cycle Time) × 100%. Frequency represents cycles per second, calculated as 1/Cycle Time. At 0% duty cycle, the signal is perpetually off; at 100%, it remains continuously on. These interconnected parameters form the mathematical foundation for all PWM applications.

Pulse Width Modulation (PWM) is a technique used to control power delivered to electrical devices. The key concepts include: (1) Period - the total time for one complete waveform cycle; (2) Frequency - calculated as 1 divided by the period, representing how many cycles occur per second; (3) Duty Cycle - the percentage of time the signal is high (on-time) versus low (off-time). A 100% duty cycle means the signal is always high (3.3V), while 50% creates a square wave alternating equally between on and off states. Increasing the duty cycle increases the average output voltage, while decreasing it reduces the voltage.

PWM (Pulsweitenmodulation) is a technique where voltage is rhythmically switched on and off. The period (T_PWM) determines the frequency (e.g., 100 μs = 10 kHz). Within each period, the voltage is on for T1 (on-time) and off for T_aus (off-time). The duty cycle (Aussteuerung, 'a') is the ratio T1/T_PWM, ranging from 0 to 1. This ratio determines the average voltage delivered to the load, enabling precise control of electrical machines.

Pulse Width Modulation (PWM) is a digital control technique where a signal's voltage switches between two levels at a constant frequency, with the pulse width (active time) varied to control average voltage; key parameters include pulse (active time), pause (inactive time), period (complete cycle), frequency (periods per second in Hz), and duty cycle (pulse width percentage of total period), enabling applications like dimming lights where brightness depends on the duty cycle ratio.

PWM is an electronic technique where a DC voltage is switched on and off at a fixed frequency, creating a signal with two states: High and Low. The period duration (T) is the reciprocal of frequency (f). The key feature is variable pulse width - the length of the high pulse can be adjusted. The duty cycle (P) is the ratio of high time to total period. The average voltage equals duty cycle multiplied by the high voltage. Typical frequencies range from hundreds to thousands of Hz (e.g., 14 kHz). This fundamental principle enables precise control of average power delivery through time-averaged voltage.

Interrupt Service Routines (ISRs) are special functions declared with the __interrupt specifier in XC8 C. The syntax is void isr_name(void) __interrupt [priority_level], returning void since hardware interrupts don't return values. ISRs handle interrupts by jumping to a predefined vector address. The compiler manages register saving and restoration. Priority levels are specified as high_priority or low_priority; if unspecified, it defaults to high priority. After handling an interrupt, the corresponding flag bit must be manually cleared before exiting, or the microcontroller will re-enter the ISR infinitely.

This lesson explains how to implement interrupt service routines (ISR) in AVR microcontrollers using internal pins. The instructor demonstrates an 8-step process: (1) consult the datasheet to identify the PCINT register for the desired pin, (2) configure the PCMSK register to enable the interrupt, (3) include the avr/interrupt.h library, (4) enable global interrupts using sei(), (5) define the ISR function with the ISR() keyword and appropriate vector name (e.g., ISR(PCINT31_vect)), (6) write the interrupt handling code, (7) configure the pin as input/output as needed, and (8) implement the main program logic. The example shows toggling LEDs at different intervals using interrupts, demonstrating how ISRs allow the microcontroller to respond to specific events while continuing other tasks.

When a timer overflows, the corresponding TF bit is set, triggering an interrupt. The CPU automatically clears the TF bit before transferring control to the interrupt vector address. Timer 0 uses vector address 000BH and Timer 1 uses 001BH. The user-defined Interrupt Service Routine (ISR) executes at these addresses. After completing the ISR, the RETI instruction returns control to the main program, resuming normal execution.

Microcontrollers execute instructions sequentially from flash memory, which works only when environments are perfectly predictable. Real-world applications require reacting to unpredictable events like button presses. Polling periodically checks for events but wastes CPU cycles, creates variable latency, and prevents low-power operation. Interrupts solve these problems by providing hardware signals that pause normal execution to handle events immediately. The CPU automatically saves its state (program counter, stack pointer, status registers) before jumping to the interrupt service routine (ISR). The interrupt vector table maps interrupt types to their ISRs. ISRs save additional registers, execute handler code, then restore state and return. Implementing GPIO interrupts requires disabling the watchdog, configuring pins for input, setting trigger edges, clearing flags, and enabling global interrupts. Variables modified in ISRs must be volatile to prevent compiler optimization. Creating abstraction layers improves maintainability: functions accept pin numbers, trigger types, and ISR function pointers. Data structures store registered ISRs per pin. On architectures like MSP430, all pins on a port share one interrupt vector, requiring shared ISRs that check individual flags and dispatch to registered handlers.

This section covers interrupt enable configuration and ISR structure. The TMR0IE bit enables Timer Zero interrupts, but GIE (global interrupt enable) and PEIE (peripheral interrupt enable) must also be set. The ISR is declared with 'interrupt' keyword and must have the signature 'void isr_timer0()'. All interrupts route to vector 0x04, so the ISR must check flags to identify which interrupt occurred. The instructor emphasizes that interrupts are disabled during ISR execution to prevent nesting, requiring GIE to be cleared at ISR entry and restored before return.