ESP32 Ghost Laps: Solving WiFi EMI Interference on a Slot Car Track

In high-speed PCB design, decoupling capacitors must be placed as close as possible to the VDD and VSS pins of each chip, rather than randomly scattered across the board, to minimize loop inductance and ensure stable power delivery; for BGA packages requiring numerous decoupling capacitors, they should be clustered near the package and connected directly to power/ground vias on adjacent layers to maintain low inductance paths, which also helps reduce ground bounce and I/O noise on signal edges.

This comprehensive section covers two interconnected aspects of PCB design: grounding fundamentals and decoupling capacitor placement. Ground serves fundamentally different purposes in signal integrity versus EMC design—in signal integrity, ground is a path for returning currents to their source, while in EMC design, ground serves as a legitimate zero-volt reference point. Three distinct types of ground exist: safety ground (earth connection for personnel protection), EMC ground (local zero-volt reference for emissions control), and digital/analog ground (return paths for specific signal types). The common practice of separating analog and digital grounds stems from misleading datasheet pin naming conventions rather than actual design requirements. Regarding decoupling, research demonstrates that when power and ground planes are closely spaced (10 mils or less), capacitor location becomes irrelevant—all capacitors contribute equally due to inherent plane capacitance. With widely spaced planes (40 mils or more), capacitor location becomes critically important—the closest capacitor does most of the work. Connection inductance, not physical distance, determines effectiveness: capacitors connected through high-inductance paths bounce energy back and forth multiple times before contributing significantly.

Effective PCB design requires proper grounding and capacitor placement. Power and signal grounds should connect at a single point (star ground) to prevent noise coupling. High-current paths should be kept separate from sensitive signal paths. Blocking capacitors should be placed close to the components they protect: low-frequency capacitors (100 μF) can be placed anywhere, but high-frequency capacitors (100 nF) should be near sensitive ICs. Components with Schmitt triggers, counters, and microcontrollers are particularly sensitive to power supply ripple and may require individual decoupling capacitors. For high-speed circuits, capacitors should be mounted directly on top of ICs to minimize inductance.

This section presents solutions for two major PCB layout problems. First, moving all external connectors to the same board edge and repositioning high-speed circuitry away from connectors prevents cables from acting as dipole antennas. Second, replacing global decoupling with local decoupling by placing capacitors at each active device's power pins (for boards with widely spaced planes) ensures current is sourced locally during transients. The solution requires identifying which plane is farthest from components and placing capacitors accordingly with vias adjacent to mounting pads.

Proper ground plane design prevents ground loops and ensures stable return paths. Avoid routing RF signals over gaps or slots in ground planes, and ensure solid ground planes under ICs. Use solid fill patterns rather than hatched patterns for lower impedance, and implement via stitching with spacing of λ/20 to λ/10. For decoupling, place capacitors beneath power pins to minimize loop area, use parallel capacitors for broad frequency coverage, and add dedicated vias connecting to power/ground planes. Use via-in-pad techniques for BGAs, filling vias with non-conductive epoxy. Smaller capacitors with lower ESL perform better than larger ones, and placing capacitors closer to vias minimizes inductive paths.

The system uses filters and circuit networks to create latching mechanisms. When boxes are empty, filters activate to load material; when non-empty, they disable and enable other inserters. The bad uranium inserter uses stack size 1 and filters only on bad uranium, creating a latch that prevents new uranium loading when bad uranium is present. This serves as an indicator of machine activation state. The system only becomes full on the first cycle, then enters stable cycling. The final inserter activates only when specific boxes are empty, ensuring preferential product loading and continuous cycling.

The SCR triggers when a positive current pulse is applied to the gate terminal, causing the device to turn on and conduct current from anode to cathode. Once triggered, the SCR remains in the on state (latched) even after the gate signal is removed. The only way to turn off an SCR is to reduce the anode current to zero, which breaks the latching condition. This behavior makes SCRs ideal for power control applications where sustained conduction is needed. The SCR's composition of alternating P and N layers creates the PNPN structure that enables this latching behavior.

Beyond simple cheat code triggers, sequential triggers (time bombs) use finite state machines to detect complex input patterns spread across multiple clock cycles. These patterns may appear non-consecutively over extended periods, making detection significantly more challenging than simple combinational triggers. The distributed nature of these triggers reduces the probability of accidental discovery during testing, as the required input sequence is unlikely to occur naturally in normal device operation.

The transistor latching mechanism uses transistors T5 and Q2 to maintain a triggered state. When a voltage variation occurs, the capacitor charges and the differentiation circuit generates a pulse. This pulse polarizes transistor T5, which in turn polarizes transistor Q2. Once polarized, Q2 maintains the circuit in a triggered state even after the original voltage variation has disappeared. The reset circuit uses a switch (S2) connected to +9V through a resistor. When pressed, the switch connects the reset point to +9V, polarizing transistor T9, which then saturates and pulls the reset point to -9V, cutting off transistors T8 and Q3. The negative voltage detection circuit is similar to the positive detection circuit but with inverted input connections. When the input voltage drops below the reference voltage (0V), the output goes to a high state, activating the detection circuit.

This segment addresses the critical challenge of maintaining state in PLC control systems. The instructor explains why momentary buttons require front edge detection (R3 block) to capture the exact moment of button press, producing a brief pulse lasting one cycle. The video demonstrates the problem: using this pulse directly to control the boiler causes it to turn off after one cycle. The solution is introduced using the SR latch (RS3 block), which maintains output state after the triggering event. The Set input latches the boiler on, while the Reset input turns it off. This establishes the fundamental pattern for implementing latching relays in PLC programming.

EMC (Electromagnetic Compatibility) standards ensure that electronic devices do not generate excessive electromagnetic interference (EMI) and are immune to interference from other devices, with key compliance tests including conducted immunity/emission, radiated immunity/emission, and ESD testing, where manufacturers must demonstrate product compliance with region-specific standards like FCC for US markets or CE for European markets before product release.

This video explains the major EMC testing standards for consumer electronics products, covering radiated immunity (IEC 61000-4-3 for RF electromagnetic field immunity, IEC 61000-4-39 for immunity to nearby RF transmitters, IEC 61000-4-8 for power frequency magnetic field immunity) and radio emission (CISPR 11 for industrial/scientific/medical equipment, CISPR 32 for multimedia equipment, FCC Part 15 for US market compliance). These tests ensure electronic devices can function reliably in electromagnetic environments while not causing interference to other devices.

This comprehensive process covers FCC and CE certifications for electronic devices. FCC enables US market sales while CE covers Europe. Testing encompasses four categories: conducted/radiated emissions (checking what devices emit) and conducted/radiated immunity (checking how devices respond to interference). The process involves radiated emissions testing in electromagnetically isolated chambers using advanced $200,000 antenna systems scanning multiple frequencies. Quasi-peak detection identifies peak signals across all orientations. Radiated immunity subjects devices to electromagnetic fields while monitoring operation. Conducted immunity applies high voltage bursts (up to 2,000V) to power supplies. Magnetic field immunity uses coils at various orientations, and ESD testing applies 8,000V. Costs range from $9,600 for first-attempt success to $25,000-$50,000 with retesting.

Electromagnetic Compatibility (EMC) ensures electronic devices don't interfere with each other and is composed of three main tests: Conducted Emissions (measured via LISN network using EN55032/CISPR22/FCC Part 15 standards), Radiated Emissions (tested in anechoic chambers with rotating antennas at 3m distance), and Electrostatic Discharge (ESD) testing (IEC 61000-4-2 at 4kV/8kV). Compliance requires a Declaration of Conformity, which can be self-certified or third-party certified. Additional standards include surge immunity (EN61000-4-5), fast transient testing (EN61000-4-4), and harmonic limits (EN61000-3-2) for equipment over 75W.

Electronic products sold commercially must comply with electromagnetic compatibility (EMC) standards specific to their target markets, including CE marks for Europe, FCC for America, and C-tick for Australia. These standards ensure products don't interfere with other devices or communications systems. Testing against these standards can cost thousands to tens of thousands of dollars, making pre-compliance testing essential. Products emit interference through four coupling mechanisms: radiative emissions (broadband noise from switching signals radiating through air via PCB traces), conductive emissions (noise conducted along cables), capacitive coupling (near-field electric field coupling), and inductive coupling (near-field magnetic field coupling). Most products are tested for radiative and conductive emissions, while capacitive and inductive coupling are only required in specific cases.