Fetch-Decode-Execute Cycle: CPU Registers and ALU Explained

Interrupts are hardware signals that pause normal execution to handle external events. The CPU saves its state (program counter, stack pointer, status registers) before jumping to the interrupt service routine (ISR). The interrupt vector table maps interrupt types to their ISRs. ISRs save additional registers, execute handler code, then restore state and return. Hardware handles state saving while software implements the actual event handling logic.

Processors execute instructions in a three-stage loop called the instruction cycle: fetching an instruction from main memory or cache, decoding it, and then executing it. At the end of each iteration, the processor checks the state of a dedicated pin called the interrupt request signal. When a hardware interrupt needs servicing, the interrupt controller sends the interrupt request signal over this line. The processor detects this signal at the end of the current instruction cycle and immediately sends back an acknowledge signal to the interrupt controller.

An interruption or trap is a disruption in the CPU's normal instruction execution flow. Vendors use different terminology for these concepts. There are two types: synchronous interrupts (traps/exceptions) caused by instruction failures like invalid memory access or invalid register usage, and asynchronous interrupts (interrupt requests) caused by hardware devices signaling service needs like disk completion or timer overflow. When the CPU receives an interrupt, it must save the complete execution state to memory including the program counter, processor status register, memory management unit state, and CPU-specific status information. The CPU then loads the program counter with a special address (interrupt vector) pointing to an interrupt handler subroutine. After the handler completes, the CPU restores all saved state before resuming the interrupted program.

The CPU interrupt cycle is a mechanism that handles interruptions during process execution. When a user creates a new request, an interrupt occurs. The CPU decides between instruction cycle and interrupt cycle based on the interrupt flip-flop status. When the flip-flop is one, the CPU stores the return address at location zero, branches to address one for the interrupt handler, resets the interrupt enable flag and flip-flop, then returns to the initial state to process the new interrupt instruction. This ensures the interrupted process can resume later.

This section introduces the fundamentals of assembly language and CPU architecture. The instructor explains that assembly language is used to edit programs without source code, working directly with machine instructions. CPU registers are introduced as the fastest storage locations in a computer, faster than RAM and disk drives. Registers are used for temporary data storage during program execution, particularly for values that need to be accessed multiple times in succession. The main registers discussed include EAX, EDX, ECX (general-purpose registers), ESP (stack pointer), EBP (base pointer), ESI, and EDI (stack-related registers), along with EIP (instruction pointer) which tracks the current execution address.

This section introduces assembly language programming concepts and prerequisites. An instruction is an action that determines what the computer must perform at a specific instant, written using operation codes (opcodes) and operands. Assembly instructions perform mathematical/logical operations, data movement, input/output, conditional execution, and loop control. Registers facilitate instruction execution, functioning similarly to variables in high-level languages. Intel/AMD processors contain two register types: general-purpose registers for data storage and movement, and special-purpose registers managed by control units. The course is based on the book 'Programação em Assembly IBM PC 8086/8088' and requires knowledge of number systems (decimal, binary, hexadecimal), binary arithmetic, and basic processor architecture.

Assembly language is a low-level programming language that directly communicates with the processor hardware, using specific registers (AX, BX, CX, DX) for data manipulation and operations. A complete assembly program requires a structured format including a model (memory allocation), stack (data storage), data segment (variable declarations), and code segment (instruction execution). The MOV instruction assigns values to registers, while ADD performs arithmetic operations. To display output, programs use DOS interrupt 21H with function 09H for string display and 01H for character input. A critical concept is ASCII code conversion: keyboard input is stored as ASCII values (e.g., '0' is 48 decimal), requiring subtraction of 30H to convert to actual numeric values for calculations.

This tutorial introduces 6510/6502 assembly language programming using Turbo Macro Pro assembler on real Commodore hardware, covering essential concepts including memory addressing (with the origin directive *), labels for code organization, fundamental opcodes like INC (increment) and JMP (jump), and understanding CPU registers (program counter, accumulator, X/Y registers, stack pointer). The video demonstrates writing a simple endless loop program that cycles through border colors by incrementing memory location $D020, illustrating how assembly language provides direct hardware control while requiring careful memory management and understanding of the two-pass assembly process.

Four addressing modes: immediate (#46), direct (address), indirect ([address]), indexed (base+index). Data movement: LDD, STO, MOV, LDX. I/O: IN, OUT. Control flow: CMP, JP, JPN. Arithmetic: ADD, SUB, INC, DEC. Shifts: LSL, LSR. Bitwise: AND, XOR, OR. Each instruction manipulates CPU registers and memory according to its specific operation.

RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) represent two fundamentally different approaches to processor design, differing primarily in how bits are allocated between the operation code (opcode) and operand fields within the current instruction register; RISC allocates fewer bits to the opcode (typically supporting 70-80 instructions) and more to the operand, enabling simpler, faster-executing instructions that require more code but fewer clock cycles per instruction, while CISC allocates more bits to the opcode (supporting up to 150+ instructions) and fewer to the operand, enabling more complex single-instruction operations but requiring more clock cycles per instruction; this architectural choice impacts instruction set complexity, memory usage, compiler design, hardware complexity, and application suitability, with RISC favoring high-performance applications like multimedia processing and CISC favoring cost-effective general-purpose computing.

CPUs are designed based on instruction set architecture: RISC (Reduced Instruction Set Computer) has simpler design with fewer instructions, fixed instruction length, and limited addressing modes. CISC (Complex Instruction Set Computer) has more complex design with variable instruction length and complex addressing modes. RISC supports only simple instructions like addition and subtraction, while CISC supports complex operations including branching. RISC is easier to implement with hardwired control units, while CISC requires microprogrammed control units. In RISC, one instruction completes per clock cycle, while CISC may execute multiple instructions per cycle. The ALU in RISC can only perform operations between two registers, while CISC allows memory-memory operations. RISC has fewer registers because it permits direct memory access. RISC processors are preferred for pipeline implementation due to their simpler instruction set, fixed instruction length, and limited addressing modes.

RISC (Reduced Instruction Set Computer) architecture uses simpler, fewer instructions that execute faster, while CISC (Complex Instruction Set Computer) uses more complex, powerful instructions; despite requiring 50% more instructions, RISC systems can run 3-4 times faster because each instruction executes in fewer clock cycles, making RISC more efficient for modern microprocessors where Moore's Law enables faster clock speeds.

RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) are two fundamental processor architecture paradigms distinguished by their instruction set design: RISC uses a smaller, fixed-length instruction set with simple operations that execute in one clock cycle, employing register-to-register operations and hardwired control units, resulting in lower hardware complexity and cost; whereas CISC uses a larger, variable-length instruction set with complex operations that may span multiple clock cycles, supporting direct memory-to-memory operations and microprogrammed control units, offering greater flexibility but at higher hardware cost and complexity.

This segment covers the fundamental differences between RISC (Reduced Instruction Set Computing) and CISC (Complex Instruction Set Computing) processor architectures. RISC processors are simpler and execute instructions faster by avoiding backward compatibility overhead, while CISC processors like Intel's x86 accumulated decades of instruction set complexity. The evolution traces from 1970s/80s computers with limited RAM where CISC's complex instructions were advantageous for code size reduction, to the 1990s when increased RAM made RISC's optimized architecture more appealing. Key implementations discussed include PowerPC (Apple), MIPS (DeskStation Tyne, SGI), DEC Alpha, and SPARC. The segment concludes with ARM's emergence from Acorn's BBC Micro, highlighting how reduced power consumption made RISC viable for mobile devices despite questionable performance gains.

A microprocessor (CPU) is the brain of a computer that executes operations, communicating with memory (RAM/ROM) and I/O devices through three types of buses: the Data Bus (bidirectional data transfer), the Address Bus (unidirectional memory location specification), and the Control Bus (signals for device coordination). The CPU's performance depends on clock frequency (operations per second), bus width (data transfer capacity), and register size (internal storage capacity), while cache memory provides faster temporary storage closer to the CPU than main memory.

A bus is a group of wires transmitting information between functional units in parallel. Three bus types exist: Address Bus (carries address information), Data Bus (carries actual data), and Control Bus (carries control signals). Single Bus Organization uses one shared bus (cheaper but sequential communication), while Multiple Bus Organization uses separate buses (more expensive but enables simultaneous data transmission). Three factors affect performance: Hardware Design (processor architecture), Instruction Set Architecture (RISC vs CISC), and Compiler (optimization techniques). Cache memory improves performance by storing frequently accessed data in fast memory near the processor. The processor clock controls instruction execution, with clock cycle (P) being the time interval and clock rate (R = 1/P) measured in cycles per second. The basic performance equation is T = (N × S) / R, where T is execution time, N is number of instructions, S is cycles per instruction, and R is clock rate.

Memory hierarchy organizes storage from fastest to slowest: Registers (inside CPU, nanosecond access), Cache memory (L1/L2, nanosecond access), Main Memory/RAM (tens of nanoseconds), and Mass Storage (milliseconds). RAM stores programs and data currently in use, containing the actual working data for the CPU. Cache is a small, fast copy of frequently accessed RAM data, maintained to speed up access. Cache does not contain independent data—it only holds copies of RAM data the CPU has recently accessed. The CPU bus system includes Address Bus (carries memory addresses), Data Bus (transfers data), and Control Bus (signals read/write operations). The Control Bus operates at slower speeds (around 200 MHz) than the CPU clock (2-4 GHz) because memory operations take longer.

Registers are the fastest memory in a computer system, used for temporary storage of data and instructions during processing. They are small in capacity but provide the highest speed for data access. The three main components of a microprocessor are the Control Unit, ALU, and Registers. Cache memory is a high-speed memory located between the CPU and main memory (DRAM). It serves as a buffer to speed up data access. When the CPU needs data, it first checks the cache. If the data is found (cache hit), it is retrieved quickly. If not (cache miss), the data is fetched from main memory and stored in cache for future access. Cache memory is made of Static RAM (SRAM), which is faster than Dynamic RAM (DRAM) used for main memory. Buses are communication pathways that transfer data, addresses, and control signals between CPU components. There are three types: Data Bus (transfers actual data), Address Bus (carries memory addresses), and Control Bus (carries control signals that coordinate operations).

CPU architecture includes Cache Memory (small, high-speed memory near CPU storing frequently used data with three levels: L1, L2, L3), and System Buses (communication channels). System Buses consist of: Data Bus (transfers actual data bidirectionally, width determines capacity), Address Bus (carries memory addresses unidirectionally from CPU to memory), and Control Bus (manages read/write operations and data transfer direction). Buses can be Serial (one bit at a time, slower, cheaper like USB) or Parallel (multiple bits simultaneously, faster, more expensive).