MOSFET Working Principle: Semiconductor Physics Explained

This comprehensive section establishes the foundational concepts of MOSFET small-signal analysis and three fundamental amplifier configurations essential for analog circuit design. The constant current biasing technique involves sensing bias current, comparing it with a reference, and adjusting gate-source voltage accordingly using four possible combinations. The three configurations are: (1) Common source with inverting gain of -g_m*R_D, (2) Common drain/source follower acting as a voltage buffer with gain ~1, and (3) Common gate functioning as a current buffer. Key parameters include: resistance looking into source is 1/gm (when r_0 >> R_D), and output resistance calculations for each configuration. The section develops the mathematical framework necessary for understanding more complex amplifier designs, establishing the relationship between small-signal parameters and circuit behavior.

The common source configuration is the most popular MOSFET amplifier topology. In this setup, the input signal is applied between gate and source, while output is taken between drain and source, making the source terminal common to both input and output for AC signals. Small-signal analysis enables determination of voltage gain, input impedance, and output impedance. The procedure involves replacing DC sources with zero, coupling/bypass capacitors with shorts, and the MOSFET with its small-signal model. This systematic approach separates DC biasing from AC signal analysis, enabling precise amplifier parameter calculation.

This comprehensive section covers MOSFET small-signal analysis and amplifier design. Key topics include: (1) MOSFET impedance characteristics - gate has infinite resistance, drain resistance (Ro) is very large, transconductance (gm) is typically much greater than 1, and source resistance is approximately 1/gm; (2) Small-signal analysis equations for both drain and source output configurations; (3) MOSFET as a terminal device with three terminals and two ports; (4) Why only three amplifier configurations are valid: Common-Source (gate input, drain output), Common-Drain/Source Follower (gate input, source output), and Common-Gate (source input, drain output). The gate cannot be an output (no current sourcing), and the drain cannot be an input (no current control in saturation).

Small-signal analysis of MOSFET amplifiers involves three key steps: first establishing the DC operating point by solving the square law equation for drain current, then linearizing the circuit around this operating point to find the transconductance gm (which equals kn' * W/L * Vov or equivalently 2ID/Vov), and finally performing linear circuit analysis using the small-signal model consisting of a voltage-controlled current source with gm and output resistance ro. The voltage gain of a common-source amplifier is approximately -gm * (RD || ro), where the negative sign indicates phase inversion. This linearized approach requires that the small-signal voltage variations be much smaller than the overdrive voltage Vov, and that the transistor remains in saturation throughout all signal excursions.

This section covers the theoretical foundations of MOSFET-based analog circuits. Operational transconductance amplifiers (OTAs) are voltage-controlled current sources more practical than direct VCVS implementations. MOSFETs operate in saturation region for maximum transconductance, with small-signal models including g_m and r_0 = 1/λ × I_D. Three fundamental amplifier configurations are presented: common source provides voltage gain with phase inversion; common drain (source follower) acts as a voltage buffer with high input impedance (~∞) and low output impedance (~1/g_m); common gate serves as a current buffer with low input impedance (~1/g_m). These configurations form the building blocks for all subsequent analog circuit designs.

Most modern logic gates are built using CMOS (Complementary Metal-Oxide-Semiconductor) technology. CMOS uses complementary pairs of p-type and n-type MOSFETs to create logic gates. This technology provides low power consumption and high noise immunity, making it the standard for modern digital electronics. The instructor explains that 90% of logic gates are built using CMOS technology. Understanding CMOS design is essential for advanced digital electronics and VLSI (Very Large Scale Integration) applications. The design process involves creating circuits that can select and route signals based on control inputs.

CMOS (Complementary Metal Oxide Semiconductor) logic gates utilize complementary pairs of NMOS and PMOS transistors, where PMOS transistors form the pull-up network and NMOS transistors form the pull-down network. This complementary configuration ensures that only one transistor conducts at any given time, eliminating the direct path from supply to ground and resulting in extremely low static power consumption. The design principle follows that NMOS transistors pass strong logic 0 but weak logic 1, while PMOS transistors pass strong logic 1 but weak logic 0, making them ideal for complementary roles. This architecture enables the implementation of basic gates (NOT, NAND, NOR) and complex gates (AND, OR, XOR, XNOR) with full voltage swing and high noise margin.

This comprehensive lecture covers the fundamentals of CMOS (Complementary Metal-Oxide-Semiconductor) technology, the cornerstone of modern digital electronics. The video explains how all digital circuits are constructed from ten basic building blocks called logic gates, which operate on binary principles where 0 represents an open switch (no current flow) and 1 represents a closed switch (current flow). The core technology relies on MOS transistors—three-terminal devices acting as controllable resistors—where the gate-source voltage controls whether a conducting channel forms in the semiconductor substrate. The lecture distinguishes between N-channel and P-channel transistors, explaining their complementary behavior: NMOS conducts when VGS exceeds threshold voltage, while PMOS conducts when VGS falls below negative threshold. The video demonstrates how these complementary pairs enable reliable digital switching, with outputs always connected to defined voltage levels (supply or ground) rather than floating. It then systematically presents three fundamental CMOS logic gates: the inverter (NOT), which produces the logical opposite of its input; the NAND gate, which outputs 0 only when both inputs are 1; and the NOR gate, which outputs 1 only when both inputs are 0. Each gate is constructed using four transistors arranged in complementary configurations, with PMOS transistors connected in series and NMOS transistors in parallel. The lecture concludes by establishing that CMOS technology enables efficient implementation of complex digital circuits through standardized, scalable gate structures.

Digital IC design uses logic gates built from transistors. A CMOS inverter consists of one pMOS transistor connected to power and one nMOS transistor connected to ground. When input is low (0), pMOS conducts and output goes high (1); when input is high (1), nMOS conducts and output goes low (0). This complementary design minimizes power consumption. The technology has advanced from the 4004 microprocessor (1971, 2,300 transistors) to modern chips with 50 billion transistors, demonstrating exponential growth in computing capability.

CMOS (Complementary Metal-Oxide-Semiconductor) technology uses pairs of NMOS and PMOS transistors to implement digital logic circuits, where NMOS transistors pull signals down to ground when the gate voltage is high, while PMOS transistors pull signals up to the supply voltage when the gate voltage is low; this complementary switching action enables the simplest logic gate—the NOT gate—to be implemented with one PMOS and one NMOS transistor connected in series between the power supply and ground, ensuring that only one transistor conducts at any given time to prevent short circuits and enable efficient signal inversion.

This section introduces the fundamental difference between ideal and non-ideal MOS transistor behavior. In ideal models, I-V characteristics show linear current increase followed by constant saturation. However, in reality, short-channel transistors (less than 1 micron) exhibit three key deviations: (1) Lower current for any given VDS value; (2) Reduced current increase when VGS increases (not proportional to VGS²); (3) Linear current rise in saturation region instead of constant. These non-ideal effects become significant as transistor dimensions shrink, particularly in modern nanometer-scale technologies like 65nm nodes with effective channel lengths around 50nm.

Short Channel Effects (SCE) become significant as transistor dimensions decrease. Channel Length Modulation (CLM) describes how the effective channel length decreases with increasing drain-source voltage, modeled as ΔL/L = λ × V_DS. This effect modifies the saturation current equation to include a (1 + λV_DS) term. The source supplies charge carriers while the drain collects them, with current flowing opposite to electron flow in NMOS devices.

Four critical non-ideal effects in VLSI devices: (1) Channel length modulation causes drain current increase in saturation region, only in short-channel devices (<200nm); (2) Velocity saturation reduces current below ideal predictions, more pronounced in short-channel devices; (3) Mobility degradation affects both short and long channel devices; (4) Drain-induced barrier lowering (DIBL) causes leakage current even when transistor should be off, only in short-channel devices. These effects are particularly relevant in modern technology nodes (180nm, 130nm, 65nm) where devices are in nanometer range.

This section covers short channel effects that emerge as MOSFET dimensions approach nanometer scales. Drain-Induced Barrier Lowering (DIBL) occurs when source and drain depletion regions overlap, reducing the potential barrier that normally prevents current flow. This causes two problems: (1) Leakage current flows between source and drain even when transistor is nominally off, increasing power consumption; (2) Channel length modulation effect becomes more pronounced. Channel length modulation occurs when drain-source voltage causes the depletion region to expand into the channel, effectively shortening the channel length and reducing resistance. This causes saturation current to increase with drain voltage, modeled by adding a (1 + λVDS) term to the saturation current equation. These effects degrade transistor performance as ideal current-source behavior breaks down in short-channel devices.

Short-channel transistors exhibit several effects that are negligible in long-channel devices. Mobility degradation causes carrier velocity to increase less than linearly with electric field. Velocity saturation occurs when carrier velocity reaches a maximum regardless of further field increases. Drain Induced Barrier Lowering (DIBL) causes threshold voltage to decrease with increasing drain voltage. These effects fundamentally change transistor behavior from the ideal square-law model and must be included in accurate circuit simulation.