Building an OS: BIOS Interrupts and Conditional Jumps

Protected mode eliminates BIOS interrupt usage, causing triple faults when attempted—a catastrophic error triggering processor reset. The VGA controller (address 0xB8000 in text mode) provides basic graphics without drivers: each character uses two bytes (ASCII + color attributes). Color bytes combine foreground (lower 4 bits) and background (upper 4 bits) colors. Switching back to real mode requires jumping to 16-bit code segments, loading 16-bit data registers, clearing the protected mode bit in CR0, and re-enabling interrupts. This bidirectional switching capability demonstrates protected mode's flexibility for OS development.

To display text on screen in low-level code, characters are written directly to video memory at address 0xb8000. Each character is represented by two bytes: one for the ASCII value and one for attributes. The MOV instruction writes this data to video memory, creating visible output on the display.

Hardware interrupts must be disabled during GDT loading: (1) Use CLI (Clear Interrupt Flag) instruction to disable interrupts, (2) Load the GDT while interrupts are disabled, (3) Use STI (Set Interrupt Flag) to re-enable interrupts after GDT loading, (4) If an interrupt occurs during GDT loading, the CPU crashes. Video output in protected mode uses direct memory access: (1) Text mode video memory starts at 0xB8000, (2) Each character position requires 2 bytes (1 byte for color attributes, 1 byte for character), (3) Color attributes: 4 bits for background (0-15), 4 bits for foreground (0-15), (4) Default color is 0x07 (black background, light gray foreground), (5) Character position calculation: Address = 0xB8000 + (row × 80 + column) × 2.

Load GDT using LGDT instruction, then perform far jump to switch segments from default (0) to code segment. In 64-bit VGA mode, each character requires 2 bytes: background color (first nibble) and foreground color (second nibble). Video memory is at 0xB8000. For example, 0x0F54 prints 'T' with white text on black background. To clear the screen, write 500 characters of background color using REP STOSD with EAX set to the color and ECX set to 500. Text output requires characters to be written in reverse order (last character first) because VGA mode prints left-to-right.

This segment covers reading the kernel from disk using BIOS interrupt 13h (INT 13h). The interrupt requires setting AH=0x02 (read function), AL=number of sectors, CH=cylinder, CL=sector, DH=head, DL=drive number (0x80 or 0x81), and ES:BX=destination buffer. The kernel is read from the beginning of the disk (cylinder 0, sector 0, head 0) to a memory address calculated using segment:offset addressing. The bootloader checks the carry flag for errors and prints status messages. The kernel is loaded at address 0x2000 (segment 0x200, offset 0x0000). The bootloader then jumps to this address to execute the kernel. Real mode memory addressing uses (segment << 4) + offset to calculate effective addresses.

This video demonstrates how to read additional disk sectors beyond the initial 512-byte boot sector using BIOS interrupt 13/AH=2 in 16-bit real mode assembly language. The process involves understanding cylinder-head-sector (CHS) addressing, setting up the ES:BX memory buffer pointer, configuring the AL register for the number of sectors to read, and using the carry flag to check for read errors. The tutorial shows how to create a simple bootloader that loads a kernel from the second sector of a floppy disk into memory at address 0x1000 and then jumps to execute it, effectively transforming a basic boot sector into a functional bootloader that can load an operating system.

To read disk sectors beyond the boot sector in x86 real mode, use BIOS interrupt 13H with CHS addressing (cylinder-head-sector), where AH=2 specifies the read operation, AL holds the number of sectors to read, CH and CL hold the cylinder and sector numbers respectively, DH holds the head number, DL holds the drive number, and ES:BX points to the memory destination; error checking involves verifying the carry flag and ensuring the correct number of sectors were actually read.

This section explains the multi-stage boot loader architecture. The boot sector (512 bytes at 0x7C00) loads the second stage from disk. The second stage performs tasks like clearing the screen, hiding the cursor, printing strings, setting up the GDT, and transitioning to protected mode. The kernel runs at a fixed address (0x9000) and prints text directly to video memory. Key implementation details include: sector boundary alignment using linker expressions, padding to 512-byte boundaries, and ensuring proper memory layout for each stage.

This tutorial demonstrates how to implement disk reading functionality in a bootloader using BIOS interrupt 13h, covering the conversion from Logical Block Addressing (LBA) to Cylinder-Head-Sector (CHS) addressing required by BIOS functions, error handling with retry mechanisms, and practical debugging techniques using Bochs emulator. The implementation shows how to read additional operating system modules from floppy disk sectors beyond the initial 512-byte boot sector, enabling the creation of multi-module operating systems.

This section explains how the Interrupt Descriptor Table (IDT) is configured to handle all types of interrupts in an operating system. The IDT contains 32 entries, each pointing to a specific ISR function that handles a particular interrupt or exception. The set IDT gate function uses the lidt assembly instruction to load the IDT into the CPU. When the CPU encounters an interrupt, it looks up the corresponding ISR in the IDT and executes that function. This mechanism allows the operating system to handle various interrupt types including hardware interrupts (keyboard, mouse, clock ticks) and software exceptions (division by zero, breakpoints).

The processor locates interrupt handler routines using the Interrupt Descriptor Table (IDT), a memory-resident table pointed to by the IDTR register. Each IDT entry contains a segment selector (16 bits) and offset (32 bits). The segment selector indexes into the GDT/LDT to obtain the code segment base address, which combines with the offset to form the final handler address. Intel x86 systems support 256 interrupt vectors (0-255): vectors 0-31 are internal processor exceptions (0-20 for faults/aborts), while vectors 32-255 are user-definable for custom hardware or software interrupts. This architecture enables flexible interrupt handling where the OS can configure specific interrupt vectors for different hardware devices and system events.

This comprehensive segment covers the complete implementation of the Interrupt Descriptor Table (IDT) and exception handling in an operating system. The IDT entry structure is defined with 16-bit base, 16-bit limit, and 8-bit flags fields, packed for memory alignment. The IDT pointer structure contains a 32-bit base and 16-bit limit. The initialization process involves creating IDT structs, setting the pointer to entries, calculating the limit as 256 entries minus 1, and zeroing memory with memset. The segment demonstrates hardware communication through port I/O operations using OUTB and INB assembly instructions for keyboard controller communication at ports 0x20, 0x21, and 0xA1. The assembly ISR macro handles all exception types by clearing interrupts (CLI), pushing the error code onto the stack, jumping to a common ISR handler, and restoring interrupts (STI). The ISR handler restores CPU context by saving and restoring segment registers (DS, ES, FS, GS) and ESP. A struct called 'regs' is defined to hold CPU register values during exception handling, including CR2, DS, EDI, ESI, ESP, EBX, EDX, ECX, EAX, EFLAGS, user ESP, and SS.