KiCad Tutorial: Running Electrical Rule Check (ERC) on Schematics

Design Rule Check (DRC) verifies that the PCB layout meets all configured rules. Users run DRC through 'Design' then 'Rule Check'. The system reports any violations (e.g., clearance violations, solder mask issues). Each violation can be double-clicked to navigate to the problem location.

Design Rule Check (DRC) is the critical final validation step before PCB manufacturing. Running DRC ensures zero errors in connectivity, trace widths, clearances, and other constraints. For a one-off board, the presenter focuses on basic checks like 15 mil clearance and 10 mil trace width. For production boards, more rigorous DRC settings would be applied. The goal is to have a clean DRC report with no violations before sending files to the manufacturer.

The Design Rule Check (DRC) is an automated process that scans the entire board for violations: trace too close to another trace, via too close to a pad, copper too close to the board edge, annular ring too small, silk screen overlapping a pad. The DRC catches hundreds of potential problems in seconds. However, DRC only checks what you tell it to check. Design rules must be loaded from the fabrication house's specification sheet before the check runs. Using default rules from the layout tool instead of the fab's actual minimums causes boards to pass DRC but fail fabrication. Gerber files are the industry standard format for communicating design to fabrication houses—a set of 2D images: one for each copper layer, one for the solder mask, one for the silk screen, and one for the board outline. The drill file tells machines exactly where to drill every hole. Design for Manufacture (DFM) is the practice of designing the board not just to work electrically but to survive the assembly process without defects. Components need consistent orientation, pads need space for solder paste, fine pitch components need fiducial marks, and polarized components need clear markings.

DRC stands for Design Rule Check, which runs in the PCB editor to ensure the layout follows manufacturing and physical constraints. DRC checks various parameters including track width, clearance between traces, distance between components, via sizes, annular rings, courtyard overlap, and copper-to-edge spacing. These rules are defined in the board setup and typically align with the manufacturer's capabilities. When running DRC, designers may encounter different types of errors and warnings; some can be corrected by adjusting the board setup according to manufacturer specifications, while others may be safely ignored if they don't impact functionality.

DRC (Design Rule Check) verifies PCB designs meet manufacturing rules. DRC settings include minimum track width, minimum spacing between tracks, and minimum distance from pads to board edges. Running DRC detects violations: proximity violations (tracks too close to each other or pads), overlap violations (different layers occupying same space), and connectivity violations (broken connections). The DRC tool reports violations allowing correction before manufacturing. Text on PCBs is automatically routed as copper, with the copper pour avoiding text areas.

This section demonstrates the complete pin configuration workflow without hardware manual reference. Users learn to access the Pin Number tab showing pin names with functions and directions, and the Matrix View organizing functions by peripherals (like SPI columns for MISO2/MOSI2 pins). The Matrix View offers spreadsheet-like features including column dragging, row/column freezing, and search functionality. The section culminates in a practical conflict example using LQFP 128 package with CFD and IIC drivers, where both drivers attempt to use pins P52 and P53, triggering error messages. Users learn to identify conflicting pins through the Pin Number tab (highlighted in red) and FSP visualization.

Functional blocks should be separated on different schematic pages (USB on one page, Ethernet on another) to enable effective component classes. ERC warnings and errors must be reviewed thoroughly—errors must be resolved, warnings carefully evaluated. A clean schematic compile is essential before PCB layout. Understanding default ERC settings is crucial, particularly the single node pin error which often results from connection matrix mistakes.

Proper pin configuration is essential for ERC (Electrical Rule Check) validation. Pins must be configured as inputs, outputs, power inputs, or power outputs. Power pins (VIN, VOUT, ground) require specific power input/output types. Open collector and open drain pins need special configuration. Pins can be hidden by unchecking visibility, but keeping them visible aids error checking. The pin table feature verifies all pins are configured correctly without duplicates or missing entries.

KiCad's custom design rules feature allows designers to modify the DRC (Design Rule Checker) behavior to accommodate specific PCB design scenarios, such as allowing clearance violations between components when one is marked as 'not populate' (not to be placed), enabling more efficient space utilization in compact PCB layouts while maintaining design integrity.

Electrical Rules Check (ERC) is a validation feature in KiCad that verifies the correctness of schematic connections. Users access ERC through the menu and execute the check. The tool identifies errors such as unconnected components or incorrect wiring. Users must fix identified issues (e.g., adding missing wires) and re-run the check until no violations are reported.

Eagle supports multiple schematic sheets within a single design. Components can be added to different sheets using the add command. Nets maintain connectivity across sheets as long as they share the same net name. The net command defines connections between sheets, and the board layout automatically connects all nets with matching names regardless of which sheet they appear on. This enables organized, modular schematic designs for complex projects.

Hierarchical schematics break complex designs into manageable subcircuits using sheet symbols. Ports define input/output connections between hierarchical blocks, with direction indicators showing signal flow. Net labels are local by default; global labels connect across multiple sheets. The root schematic contains top-level blocks, with subsheets organized hierarchically. Jumping between sheets uses hierarchy navigation commands. Pin properties including direction can be edited by double-clicking components and pressing E.

Hierarchical schematics break complex designs into manageable sub-pages connected through hierarchical connectors. Using local nets only confines signals to their pages, preventing accidental connections and forcing explicit inter-page routing. Harnesses group related signals (like 64-bit buses) into single connection lines, reducing visual clutter and enabling efficient signal movement during layout optimization. Multi-instantiation allows reusing identical schematic pages (e.g., dual memory interfaces) while maintaining consistency. Net naming conventions can allow different names at each level or propagate hierarchical names including page/symbol information. Signal naming conventions should encode type, voltage, directionality, and polarity for quick understanding. This systematic approach facilitates team collaboration, automated checking, and reduces errors during design reviews and debugging sessions.

This section teaches hierarchical sheet design for managing complex circuits. Hierarchical sheets divide large circuits into multiple sheets to improve readability and organization. The process involves creating a hierarchical sheet symbol on the main (root) sheet, naming it, and specifying the source file. You then create hierarchical symbols (like V+ and V-) to serve as connection points. To interconnect sheets, use the import hierarchical pin function to position connection points and add labels like VCC and GND. Best practice is to place output connectors on the right and input connectors on the left of the hierarchical sheet.

Hierarchical schematics organize complex designs by dividing them into functional blocks connected through hierarchical connections—single wires for individual signals or buses for multiple signals. This approach improves readability for large designs. Visual enhancement techniques include adding connector pictures next to symbols, importing vector graphics, and using five predefined comment types categorized by severity. Component layout best practices place all inputs on the left and outputs on the right, following natural reading direction. Complex components like microcontrollers benefit from splitting into sub-components for clarity.